(Hong Kong)
Product Summary
The W972GG6JB-25 is a 2G bits DDR2 SDRAM, organized as 16,777,216 words × 8 banks × 16 bits. The W972GG6JB-25 achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for various applications. The W972GG6JB-25 is sorted into the following grade parts: -18, -25, 25I, 25A, 25K, -3 and -3A. The -18 of the W972GG6JB-25 is compliant to the DDR2-1066 (7-7-7) specification. The -25/25I/25A/25K of the W972GG6JB-25 are compliant to the DDR2-800 (5-5-5) or DDR2-800 (6-6-6) specification (the 25I industrial grade parts is guaranteed to support -40 ℃ ≤ TCASE ≤ 95 ℃). The -3/-3A of the W972GG6JB-25 are compliant to the DDR2-667 (5-5-5) specification.
Parametrics
W972GG6JB-25 absolute maximum ratings: (1)Average clock period: 1.875 nS; (2)Active to Read/Write Command Delay Time: Min. 13.125 nS; (3)Average periodic refresh Interval: 7.8 μS; (4)Precharge to Active Command Period: Min. 13.125 nS; (5)Active to Ref/Active Command Period: Min. 58.125 nS; (6)Active to Precharge Command Period: Min. 45 nS; (7)Operating one bank active-precharge current: Max. 90 mA; (8)Operating one bank active-read-precharge current: Max. 96 mA; (9)Operating burst read current: Max. 195 mA; (10)Operating burst write current: Max. 155 mA; (11)Burst refresh current: Max. 175 mA; (12)Self refresh current (TCASE ≤ 85 ℃): Max. 12 mA; (13)Operating bank interleave read current: Max. 310 mA.
Features
W972GG6JB-25 features: (1)Power Supply: VDD, VDDQ = 1.8 V ± 0.1V; (2)Double Data Rate architecture: two data transfers per clock cycle; (3)CAS Latency: 3, 4, 5, 6 and 7; (4)Burst Length: 4 and 8; (5)Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data; (6)Edge-aligned with Read data and center-aligned with Write data; (7)DLL aligns DQ and DQS transitions with clock; (8)Differential clock inputs (CLK and CLK); (9)Data masks (DM) for write data; (10)Commands entered on each positive CLK edge, data and data mask are referenced to both edges of DQS; (11)Posted CAS programmable additive latency supported to make command and data bus efficiency; (12)Read Latency = Additive Latency plus CAS Latency (RL = AL + CL); (13)Off-Chip-Driver impedance adjustment (OCD) and On-Die Termination (ODT) for better signal quality; (14)Auto-precharge operation for read and write bursts; (15)Auto Refresh and Self Refresh modes; (16)Precharged Power Down and Active Power Down; (17)Write Data Mask; (18)Write Latency = Read Latency - 1 (WL = RL - 1); (19)Interface: SSTL_18; (20)Packaged in WBGA 84 Ball (11 × 13 mm2), using Lead free materials with RoHS compliant.
Diagrams
