(Hong Kong)
Product Summary
The EPM9560ARC208-10N is an in-system-programmable, high-density, highperformance EPLD based on Altera third-generation MAX architecture. Fabricated on an advanced CMOS technology, the EEPROM-based EPM9560ARC208-10N provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz. The -10 speed grade of it is compliant with the PCI Local Bus Specification, Revision 2.2.
Parametrics
EPM9560ARC208-10N absolute maximum ratings: (1)VCC Supply voltage With respect to ground (2): min=-2.0V, max=7.0V; (2)VI DC input voltage With respect to ground (2): min=-2.0V, max7.0V; (3)VCCISP Supply voltage during in-system programming With respect to ground (2): min=-2.0V, max7.0V; (4)IOUT DC output current, per pin: min=-25mA, max=25mA; (5)TSTG Storage temperature No bias: min=-65℃, max=150℃; (6)TAMB Ambient temperature Under bias: min=-65℃, max=135℃; (7)TJ Junction temperature Ceramic packages, under bias: max=150℃; PQFP and RQFP packages, under bias: max=135℃.
Features
EPM9560ARC208-10N features: (1)High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX (MAX) architecture; (2)5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface; (3)Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990; (4)High-density erasable programmable logic device (EPLD) family ranging from 6,000 to 12,000 usable gates (see Table 1); (5)10-ns pin-to-pin logic delays with counter frequencies of up to 144 MHz; (6)Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2; (7)Dual-output macrocell for independent use of combinatorial and registered logic.
Diagrams
