Product Summary

The W9425G6JH-5 is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM). The W9425G6JH-5 is organized as 4,194,304 words × 4 banks × 16 bits. The W9425G6JH-5 delivers a data bandwidth of up to 500M words per second (-4). To fully comply with the personal computer industrial standard, The W9425G6JH-5 is sorted into the following speed grades: -4, -5 and -5I. The -4 of the W9425G6JH-5 is compliant to the DDR500/CL3 and CL4 specification. The -5/-5I of the W9425G6JH-5is compliant to the DDR400/CL3 specification (the -5I grade which is guaranteed to support -40 to 85 ℃).

Parametrics

W9425G6JH-5 absolute maximum ratings: (1)Input, Output Voltage, VIN: -0.5 to VDD + 0.5 V; (2)Power Supply Voltage, VDD: -1 to 3.6 V; (3)Operating Temperature, TOPR: 0 to 70 ℃; (4)Storage Temperature, TSTG: -55 to 150 ℃; (5)Soldering Temperature (10s), TSOLDER: 260 ℃; (6)Power Dissipatio, PD: 1 W; (7)Short Circuit Output Current, IOUT: 50 mA.

Features

W9425G6JH-5 features: (1)2.5V ±0.2V Power Supply for DDR400; (2)2.4V to 2.7V Power Supply for DDR500; (3)Up to 250 MHz Clock Frequency; (4)Double Data Rate architecture; two data transfers per clock cycle; (5)Differential clock inputs (CLK and CLK ); (6)DQS is edge-aligned with data for Read; center-aligned with data for Write; (7)CAS Latency: 2, 2.5, 3 and 4; (8)Burst Length: 2, 4 and 8; (9)Auto Refresh and Self Refresh; (10)Precharged Power Down and Active Power Down; (11)Write Data Mask; (12)Write Latency = 1; (13)7.8μS refresh interval (8K/64 mS refresh); (14)Maximum burst refresh cycle: 8; (15)Interface: SSTL_2; (16)Packaged in TSOP II 66-pin, using Lead free materials with RoHS compliant.

Diagrams

W9425G6JH-5 block diagram

Image Part No Mfg Description Data Sheet Download Pricing
(USD)		 Quantity
W9425G6JH-5I
W9425G6JH-5I

IC DDR SDRAM 256MBIT 66TSOPII
Data Sheet
0-1: $1.66
1-10: $1.49
10-25: $1.47
25-50: $1.46
50-100: $1.31
100-250: $1.26
250-500: $1.26
500-1000: $1.17
1000-2500: $1.15
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