Product Summary

The TMS320C6455BZTZ1 is a fixed-point digital signal processor. The TMS320C6455BZTZ1 is based on the third-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for applications including video and telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The TMS320C6455BZTZ1 is upward code-compatible from previous devices that are part of the C6000 DSP platform.

Parametrics

TMS320C6455BZTZ1 abosute maximum ratings: (1)Supply voltage range: CVDD: -0.5 V to 1.5 V; DVDD33: -0.5 V to 4.2 V; DVDDR, DVDD18, AVDLL1, AVDLL2: -0.5 V to 2.5 V; DVDD15: -0.5 V to 2.5 V; DVDD12, DVDDRM, AVDDT, AVDDA: -0.5 V to 1.5V; PLLV1, PLLV2: -0.5 V to 2.5 V; (2)Input voltage (VI) range: 3.3-V pins (except PCI-capable pins): -0.5 V to DVDD33 + 0.5 V; PCI-capable pins: -0.5 V to DVDD33 + 0.5 V; RGMII pins: -0.5 V to 2.5 V; DDR2 memory controller pins: -0.5 V to 2.5 V; (3)Output voltage (VO) range: 3.3-V pins (except PCI-capable pins): -0.5 V to DVDD33 + 0.5 V; PCI-capable pins: -0.5 V to DVDD33 + 0.5 V; RGMII pins: -0.5 V to 2.5 V; DDR2 memory controller pins: -0.5 V to 2.5 V.

Features

TMS320C6455BZTZ1 features: (1)16 General-Purpose I/O (GPIO) Pins; (2)System PLL and PLL Controller; (3)Secondary PLL and PLL Controller, Dedicated to EMAC and DDR2 Memory Controller; (4)Advanced Event Triggering (AET) Compatible; (5)Trace-Enabled Device; (6)IEEE-1149.1 (JTAG) Boundary-Scan-Compatible; (7)697-Pin Ball Grid Array (BGA) Package(ZTZ or GTZ Suffix), 0.8-mm Ball Pitch; (8)0.09-μm/7-Level Cu Metal Process (CMOS); (9)3.3-/1.8-/1.5-/1.25-/1.2-V I/Os, 1.25-/1.2-V Internal.

Diagrams

TMS320C6455BZTZ1 pin connection