Product Summary

The SN74ALVCH16373DGGR is an octal transparent D-type latch designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH16373DGGR is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.

Parametrics

SN74ALVCH16373DGGR absolute maximum ratings: (1)Supply voltage range, VCC: -0.5 V to 4.6 V; (2)Input voltage range, VI: -0.5 V to 4.6 V; (3)Output voltage range, VO: -0.5 V to VCC + 0.5 V ; (4)Input clamp current, IIK (VI < 0): -50 mA; (5)Output clamp current, IOK (VO < 0): -50 mA; (6)Continuous output current, IO: ±50 mA; (7)Continuous current through VCC or GND: ±100 mA; (8)Package thermal impedance, θJA: DGV package 92℃/W; DW package 58℃/W; GQN/ZQN package: 78℃/W; PW package: 83℃/W; (9)Storage temperature range, Tstg: -65℃ to 150℃.

Features

SN74ALVCH16373DGGR features: (1)Operates From 1.65 V to 3.6 V; (2)Max tpd of 3.3 ns at 3.3 V; (3)±24-mA Output Drive at 3.3 V; (4)Bus Hold on Data Inputs Eliminates the; (5)Need for External Pullup/Pulldown; (6)Resistors; (7)Latch-Up Performance Exceeds 100 mA; (8)JESD 78, Class II; (9)ESD Protection Exceeds JESD 22, 2000-V Human-Body Model (A114-A); 200-V Machine Model (A115-A); 1000-V Charged-Device Model (C101).

Diagrams

SN74ALVCH16373DGGR block diagram

Image Part No Mfg Description Data Sheet Download Pricing
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SN74ALVCH16373DGGR
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0-1: $0.82
1-25: $0.64
25-100: $0.58
100-250: $0.50
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1-25: $0.71
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100-250: $0.55
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