Product Summary

The SN65LVDS301ZQER is a Programmable 27-bit display serial interface transmitter. The SN65LVDS301ZQER serializer device converts 27 parallel data inputs to 1, 2, or 3 Sub Low-Voltage Differential Signaling (SubLVDS) serial outputs. It loads a shift register with 24 pixel bits and 3 control bits from the parallel CMOS input interface. In addition to the 27 data bits, the device adds a parity bit and two reserved bits into a 30-bit data word. Each word is latched into the device by the pixel clock (PCLK). The parity bit (odd parity) allows a receiver to detect single bit errors. The serial shift register is uploaded at 30, 15, or 10 times the pixel-clock data rate depending on the number of serial links used. A copy of the pixel clock is output on a separate differential output.

Parametrics

SN65LVDS301ZQER absolute maximum ratings: (1)Supply voltage range: -0.3 to 2.175 V; (2)Voltage range at any output terminal: -0.5 to 2.175 V; (3)Voltage range at any input terminal: -0.5 to 2.175 V; (4)Human Body Model(3) (all Pins): ±3 kV; (5)Charged-Device Mode(4)l (all Pins): ±500 V; (6)Machine Model(5) (all pins): ±200 V.

Features

SN65LVDS301ZQER features: (1)Bus Swap for Increased PCB Layout Flexibility ; (2)1.8-V Supply Voltage ; (3)Typical Application: Host-Controller to the bus to Display-Module Interface; (4)Pixel Clock Range of 4 MHz-65 MHz ; (5)Failsafe on all CMOS Inputs; (6)Packaging: 80 Pin 5 mm x 5 mm μBGA.

Diagrams

SN65LVDS301ZQER block diagram

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