Product Summary

The 1Gb Double-Data-Rate-3 (DDR3(L)) F-die DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM.
The 1Gb chip is organized as 16Mbit x 8 I/Os x 8 banks or 8Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 2133 Mb/ pin/sec for general applications.
The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and ?? falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion.
These devices operate with a single 1.5V ± 0.075V or 1.35V -0.067/+0.1V power supply and are available in BGA packages.

Features

? JEDEC DDR3 Compliant
- 8n Prefetch Architecture
- Differential Clock(CK/??) and Data Strobe(DQS/???)
- Double-data rate on DQs, DQS and DM
? Data Integrity
- Auto Self Refresh (ASR) by DRAM built-in TS
- Auto Refresh and Self Refresh Modes
? Power Saving Mode
- Partial Array Self Refresh (PASR)1
- Power Down Mode
? CAS Latency (5/6/7/8/9/10/11/12/13/14)
? CAS Write Latency (5/6/7/8/9/10)
? Additive Latency (0/CL-1/CL-2)
? Write Recovery Time (5/6/7/8/10/12/14/16)
? Burst Type (Sequential/Interleaved)
? Burst Length (BL8/BC4/BC4 or 8 on the fly)
Programmable Functions
? Self RefreshTemperature Range(Normal/Extended)
? Output Driver Impedance (34/40)
? On-Die Termination of Rtt_Nom(20/30/40/60/120)
? On-Die Termination of Rtt_WR(60/120)
? Precharge Power Down (slow/fast)
? Signal Integrity
- Configurable DS for system compatibility
- Configurable On-Die Termination
- ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%)
? Signal Synchronization
- Write Leveling via MR settings 7
- Read Leveling via MPR
? Interface and Power Supply
- SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V)
- SSTL_1354 for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V)