Product Summary

The MT48LC32M16A2P-75:C is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. The MT48LC32M16A2P-75:C is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 134,217,728-bit banks is organized as 8192 rows by 4096 columns by 4 bits. Each of the x8’s 134,217,728-bit banks is organized as 8192 rows by 2048 columns by 8 bits. Each of the x16’s 134,217,728-bit banks is organized as 8192 rows by 1024 columns by 16 bits.

Parametrics

MT48LC32M16A2P-75:C absolute maximum ratings: (1)Voltage on VDD/VDDQ supply relative to VSS, VDD/VDDQ: –1 to +4.6 V; (2)Voltage on inputs, NC, or I/O balls relative to VSS, VIN: –1 to +4.6 V; (3)Storage temperature (plastic), TSTG: –55 +155 ℃; (4)Power dissipation: 1 W.

Features

MT48LC32M16A2P-75:C features: (1)PC100- and PC133-compliant; (2)Fully synchronous; all signals registered on positive edge of system clock; (3)Internal, pipelined operation; column address can be changed every clock cycle; (4)Internal banks for hiding row access/precharge; (5)Programmable burst lengths: 1, 2, 4, 8, or full page; (6)Auto precharge, includes concurrent auto precharge and auto refresh modes; (7)Self refresh mode; (8)Auto refresh: 64ms, 8192-cycle refresh; (9)LVTTL-compatible inputs and outputs; (10)Single 3.3V ±0.3V power supply.

Diagrams

MT48LC32M16A2P-75:C block diagram

Image Part No Mfg Description Data Sheet Download Pricing
(USD)		 Quantity
MT48LC32M16A2P-75:C
MT48LC32M16A2P-75:C

IC SDRAM 512MBIT 133MHZ 54TSOPII
Data Sheet
0-1000: $10.26
MT48LC32M16A2P-75:C TR
MT48LC32M16A2P-75:C TR

IC SDRAM 512MBIT 133MHZ 54TSOP
Data Sheet
0-1: $16.00
1-10: $14.90
10-25: $14.73
25-50: $14.37
50-100: $12.62
100-250: $12.19
250-500: $11.86