(Hong Kong)
Product Summary
The MT46V16M16P-5B:M is a low voltage version of the DDR SDRAM. The MT46V16M16P-5B:M uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access for the MT46V16M16P-5B:M effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls.
Parametrics
MT46V16M16P-5B:M absolute maximum ratings: (1)VDD supply voltage relative to VSS, VDD: –1 to 3.6 V; (2)VDDQ supply voltage relative to VSSQ, VDDQ: –1 to 3.6 V; (3)VREF and inputs voltage relative to VSS: –1 to 3.6 V; (4)I/O pins voltage relative to VSS: –0.5 to VDDQ+0.5 V; (5)Storage temperature: –55 to 150 ℃; (6)Short circuit output current: 50 mA.
Features
MT46V16M16P-5B:M features: (1)VDD = 2.5V ±0.2V; VDDQ = 2.5V ±0.2V; (2)Bidirectional data strobe (DQS) transmitted/received with data, that is, source-synchronous data capture; (3)Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle; (4)Differential clock inputs (CK and CK#); (5)Commands entered on each positive CK edge; (6)DQS edge-aligned with data for READs; centeraligned with data for WRITEs; (7)DLL to align DQ and DQS transitions with CK; (8)Four internal banks for concurrent operation; (9)Data mask (DM) for masking write data; (10)Programmable burst lengths (BL): 2, 4, or 8; (11)Auto refresh 64ms, 8192-cycle; (12)Longer-lead TSOP for improved reliability (OCPL); (13)2.5V I/O (SSTL_2-compatible); (14)Concurrent auto precharge option supported; (15)tRAS lockout supported.
Diagrams
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 MT46V16M16P-5B:M |
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