Product Summary

The EPF10K100GC503-3 is an Embedded Programmable Logic Device. Based on reconfigurable CMOS SRAM elements, the Flexible Logic Element MatriX (FLEX) architecture incorporates all features necessary to implement common gate array megafunctions. With up to 250,000 gates, the EPF10K100GC503-3 provides the density, speed, and features to integrate entire systems, including multiple 32-bit buses, into a single device. The EPF10K100GC503-3 is reconfigurable, which allows 100% testing prior to shipment.

Parametrics

EPF10K100GC503-3 absolute maximum ratings: (1)VCCINT Supply voltage With respect to ground: –0.5 to 3.6 V; VCCIO: –0.5 to 4.6 V; (2)VI DC input voltage: –2.0 to 5.75 V; (3)IOUT DC output current, per pin: –25 to 25 mA; (4)TSTG Storage temperature No bias: –65 to 150 ℃; (5)TAMB Ambient temperature Under bias: –65 to 135 ℃; (6)TJ Junction temperature PQFP, TQFP, BGA, and FineLine BGA packages, under bias: 135 ℃; Ceramic PGA packages, under bias: 150 ℃.

Features

EPF10K100GC503-3 features: (1)Embedded programmable logic devices (PLDs), providing system-on-a-programmable-chip (SOPC) integration in a single device: Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions; Dual-port capability with up to 16-bit width per embedded array block (EAB); Logic array for general logic functions; (2)High density: 30,000 to 200,000 typical gates; Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be used without reducing logic capacity; (3)System-level features.

Diagrams

EPF10K100GC503-3 pin connection