(Hong Kong)
Product Summary
The EP2C5F256C8N contains a two-dimensional row- and column-based architecture to implement custom logic. The EP2C5F256C8N is manufactured on 300-mm wafers using the 90-nm low-k dielectric process of TSMC to ensure rapid availability and low cost. By minimizing silicon area, the EP2C5F256C8N can support complex digital systems on a single chip at a cost that rivals that of ASICs.
Parametrics
EP2C5F256C8N absolute maximum ratings: (1)On the condition of with respect to ground, VCCINT Supply voltage: min=-0.5V, max=1.8V; (2)On the condition of with respect to ground, VCCIO Output supply voltage: min=-0.5V, max=4.6V; (3)On the condition of with respect to ground, VCCA_PLL [1..4] PLL supply voltage: min=-0.5V, max=1.8V; (4)VIN DC input voltage: min=-0.5V, max=4.6V; (5)IOUT DC output current, per pin: min=-25mA, max=40mA; (6)On the condition of no bias, TSTG Storage temperature: min=-65℃, max=150℃; (7)On the condition of BGA packages under bias, TJ Junction temperature max=125℃.
Features
EP2C5F256C8N features: (1)M4K embedded memory blocks; (2)Up to 1.1 Mbits of RAM available without reducing available logic; (3)4,096 memory bits per block (4,608 bits per block including 512 parity bits); (4)Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36; (5)True dual-port (one read and one write, two reads, or two writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes; (6)Byte enables for data input masking during writes; (7)Up to 260-MHz operation.
Diagrams
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 EP2C5F256C8N |
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IC CYCLONE II FPGA 5K 256-FBGA |
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EP2C15AF256C6N |
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IC CYCLONE II FPGA 15K 256-FBGA |
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EP2C15AF256C8N |
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IC CYCLONE II FPGA 15K 256-FBGA |
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EP2C15AF484C7N |
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