(Hong Kong)
Product Summary
The EP102C is a 6/8-bit LVDS receiver. The EP102C is capable of receiving LVDS inputs at 85 Mhz clock rate. The chip of the EP102C converts the LVDS differential inputs into 18/24-bits RGB data outputs and 3 control outputs (Vsync, Hsync & DE). In 18-bit RGB applications, the 6-bit data can be output left or right justified from the 8-bit data output pins.
Features
EP102C features: (1)Wide operating frequency range: 28 to 85 Mhz pixel rate; (2)Wide channel skew tolerance: 1/3 bit time; (3)Selectable left or right justified in 6-bit data output; (4)No external components required; (5)Power Down Mode; (6)Single Power Supply (3.3V); (7)Low profile 56 Lead TSSOP Package (Pb-free).
Diagrams
