Product Summary

The ADMC300 is a single-chip DSP-based controller, suitable
for high performance control of ac induction motors, permanent
magnet synchronous motors and brushless dc motors. The
ADMC300 integrates a 25 MIPS, fixed-point DSP core with a
complete set of motor control peripherals that permits fast,
efficient development of servo motor controllers.
The DSP core of the ADMC300 is the ADSP-2171, which is
completely code compatible with the ADSP-2100 DSP family
and combines three computational units, data address generators and a program sequencer. The computational units comprise an ALU, a multiplier/accumulator (MAC) and a barrel
shifter. The ADSP-2171 adds new instructions for bit manipulation, multiplication (X squared), biased rounding and global
interrupt masking. In addition, two flexible, double-buffered,
bidirectional, synchronous serial ports are included in the
ADMC300.
The ADMC300 provides 4K ×24-bit program memory RAM,
2K ×24-bit program memory ROM and 1K ×16-bit data
memory RAM. The program and data memory RAM can be
boot loaded through the serial port from either a serial SROM/
E
2
PROM, asynchronous (UART) connection, or synchronous connection. The program memory ROM includes a
monitor that adds software debugging features through the
serial port. In addition, a number of pre-programmed mathematical and motor control functions are included in the
program memory ROM.
The motor control peripherals of the ADMC300 comprise a
high performance, five channel ADC system that uses sigmadelta conversion technology offering a typical signal-to-noise
ratio (SNR) of 76 dB, equivalent to 12 bits. In addition, a 16-bit
center-based PWM generation unit can be used to produce high
accuracy PWM signals with minimal processor overhead. The
ADMC300 also contains a flexible encoder interface unit for
position sensor feedback, two auxiliary PWM outputs, twelve
lines of digital I/O, a two-channel event capture system, a 16-bit
watchdog timer, a 16-bit interval timer and a programmable
interrupt controller that manages all peripheral interrupts

Features

25 MIPS Fixed-Point DSP Core
Single Cycle Instruction Execution (40 ns)
ADSP-2100 Family Code Compatible
Independent Computational Units
ALU
Multiplier/Accumulator
Barrel Shifter
Multifunction Instructions
Single Cycle Context Switch
Powerful Program Sequencer
Zero Overhead Looping
Conditional Instruction Execution
Two Independent Data Address Generators
Memory Configuration
4K 24-Bit Program Memory RAM
2K 24-Bit Program Memory ROM
1K 16-Bit Data Memory RAM
High-Resolution Multichannel ADC System
Five Independent 16-Bit Sigma-Delta ADCs
76 dB SNR Typical (ENOB > 12 Bits)
Arranged in Two Independently Clocked Banks
Differential or Single-Ended Inputs
Programmable Sample Frequency to 32.5 kHz