Product Summary
The 74LV164PW,112 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC/HCT164. The 74LV164PW,112 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (Dsa or Dsb); either input can be used as an active HIGH enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied HIGH.
Parametrics
74LV164PW,112 absolute maximum ratings: (1)DC supply voltage: –0.5 to +7.0 V; (2)DC input diode current VI < –0.5 or VI > VCC + 0.5V: 20 mA; (3)DC output diode current VO < –0.5 or VO > VCC + 0.5V: 50 mA; (4)DC output source or sink current – standard outputs –0.5V < VO < VCC + 0.5V: 25 mA; (5)DC VCC or GND current for types with –standard outputs: 50 mA; (6)Storage temperature range: –65 to +150 °C; (7)Power dissipation per package for temperature range: -40 to +125°C –plastic DIL above +70°C derate linearly with 12mW/K: 750 mW; (8)Power dissipation per package for temperature range: -40 to +125°C –plastic mini-pack (SO)above +70°C derate linearly with 8 mW/K: 500 mW; (9)Power dissipation per package for temperature range: -40 to +125°C –plastic shrink mini-pack (SSOP and TSSOP)above +60°C derate linearly with 5.5 mW/K: 400 mW.
Features
74LV164PW,112 features: (1)Wide operating voltage: 1.0 to 5.5V; (2)Optimized for Low Voltage applications: 1.0 to 3.6V; (3)Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V; (4)Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V, Tamb = 25°C; (5)Typical VOHV (output VOH undershoot) 2V @ VCC = 3.3V, Tamb = 25°C; (6)Gated serial data inputs; (7)Asynchronous master reset; (8)Output capability: standard; (9)ICC category: MSI.
Diagrams
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74LV164PW,112 |
NXP Semiconductors |
Counter Shift Registers 8-BIT SI-PO SHIFT |
Data Sheet |
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