(Hong Kong)
Product Summary
The 74HC125PW is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC125PW is specified in compliance with JEDEC standard no. 7A. The 74HC125PW is four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a HIGH impedance OFF-state. The “125” is identical to the “126” but has active LOW enable inputs.
Parametrics
74HC125PW absolute maximum ratings: (1)tPHL/ tPLH, propagation delay nA to nY CL = 15 pF; VCC = 5 V: 9ns; (2)CI, input capacitance: 3.5 pF; (3)CPD, power dissipation capacitance per buffer: 22pF.
Features
74HC125PW features: (1)Output capability: bus driver; (2)ICC category: MSI.
Diagrams
| Image | Part No | Mfg | Description |  |
Pricing (USD) |
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 74HC125PW |
NXP Semiconductors |
Buffers & Line Drivers QUAD 3-STATE BUS BUF |
Data Sheet |
Negotiable |
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74HC125PW,112 |
NXP Semiconductors |
Buffers & Line Drivers QUAD 3-STATE BUS BUF |
Data Sheet |
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74HC125PW,118 |
NXP Semiconductors |
Buffers & Line Drivers QUAD 3-STATE BUS BUF |
Data Sheet |
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